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HM514405D Series
1,048,576-word x 4-bit Dynamic RAM Access Memory
ADE-203-689 (Z) Preliminary Rev. 0.0 Dec. 12, 1996 Description
The Hitachi HM514405D is a CMOS dynamic RAM organized 1,048,576-word x 4-bit. HM514405D has realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM514405D offers Extended Data Out (EDO) Page Mode as a high speed access mode. Multiplexed address input permits the HM514405D to be packaged in standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin plastic TSOP II.
Features
* Single 5 V (10%) * Access time: 60 ns/70 ns (max) * Power dissipation Active mode: 715 mW/660 mW (max) Standby mode: 11 mW (max) * EDO page mode capability * 1024 refresh cycles : 16 ms * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * Test function
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specification.
HM514405D Series
Ordering Information
Type No. HM514405DS-6 HM514405DS-7 HM514405DTT-6 HM514405DTT-7 Access time 60 ns 70 ns 60 ns 70 ns Package 300-mil 26-pin plastic SOJ (CP-26/20D) 300-mil 26-pin plastic TSOP II (TTP-26/20D)
2
HM514405D Series
Pin Arrangement
HM514405DS Series HM514405DTT Series
I/O1 1 I/O2 2 WE 3 RAS 4 A9 5
26 VSS 25 I/O4 24 I/O3 23 CAS 22 OE
I/O1 1 I/O2 2 WE 3 RAS 4 A9 5
26 VSS 25 I/O4 24 I/O3 23 CAS 22 OE
A0 9 A1 10 A2 11 A3 12 VCC 13
18 A8 17 A7 16 A6 15 A5 14 A4
A0
9
18 A8 17 A7 16 A6 15 A5 14 A4
A1 10 A2 11 A3 12 VCC 13
(Top view)
(Top view)
Pin Description
Pin name A0 to A9 Function Address input - Row address - Column address - Refresh address Data input/output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground A0 to A9 A0 to A9 A0 to A9
I/O1 to I/O4 RAS CAS WE OE VCC VSS
3
4
RAS
Row Driver Row Driver
Block Diagram
HM514405D Series
RAS Control Circuit
256 k Memory Array Mat
256 k Memory Array Mat
I/O1
I/O1 Buffer
I/O Bus & Column Decoder
Row Driver Row Driver
I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat
256 k Memory Array Mat
Row Driver Row Driver
CAS
CAS Control Circuit
256 k Memory Array Mat
Row Address Buffer I/O2 I/O2 Buffer
I/O Bus & Column Decoder
Row Driver Row Driver
I/O Bus & Column Decoder 256 k Memory Array Mat
256 k Memory Array Mat
WE
WE Control Circuit
Row Decoder & Peripheral Circuit
Address A0-A9
Row Driver Row Driver
256 k Memory Array Mat
256 k Memory Array Mat I/O Bus & Column Decoder
I/O3
OE
I/O3 Buffer
OE Control Circuit
I/O Bus & Column Decoder
Row Driver Row Driver
256 k Memory Array Mat
Row Driver Row Driver
256 k Memory Array Mat 256 k Memory Array Mat
256 k Memory Array Mat
Column Address Buffer
Row Driver Row Driver
I/O4
I/O4 Buffer
I/O Bus & Column Decoder
I/O Bus & Column Decoder 256 k Memory Array Mat
256 k Memory Array Mat
HM514405D Series
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 4.5 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.5 6.5 0.8 Unit V V V V 1 1 1 Note
5
HM514405D Series
DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)
HM514405D -6 Parameter Operating current Standby current Symbol I CC1 I CC2 Min -- -- -7 Max Min 110 2 -- -- Max Unit Test conditions 100 2 mA mA RAS, CAS cycling t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS V CC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t HPC = min 0 V Vin 7 V 0 V Vout 7 V Dout = disable High Iout = -2 mA Low Iout = 2 mA 1, 3 2 1 Notes 1, 2
--
1
--
1
mA
RAS-only refresh current Standby current
I CC3 I CC5
-- --
110 5
-- --
100 5
mA mA
CAS-before-RAS refresh current EDO page mode current Input leakage current Output leakage current Output high voltage Output low voltage
I CC6 I CC4 I LI I LO VOH VOL
-- -- -10 -10 2.4 0
110 130 10 10 VCC 0.4
-- -- -10 -10 2.4 0
100 120 10 10 VCC 0.4
mA mA A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
Capacitance (Ta = 25C, VCC = 5 V 10%)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout.
6
HM514405D Series
AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V)*1, *14, *15, *16
Test Conditions * * * * * Input rise and fall time : 2 ns Input level : V IL = 0 V, V IH = 3.0 V Input timing reference levels : 0.8 V, 2.4 V Output timing reference levels : 0.8 V, 2.0 V Output load: 1 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM514405D -6 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Refresh period Symbol t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t ODD t DZO t DZC tT t REF Min 104 40 60 10 0 10 0 10 20 15 15 48 10 15 0 0 2 -- Max -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 16 -7 Min 124 50 70 13 0 10 0 13 20 15 18 58 10 18 0 0 2 -- Max -- -- 10000 10000 -- -- -- -- 52 35 -- -- -- -- -- -- 50 16 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 23 8 9 19 20 Notes
7
HM514405D Series
Read Cycle
HM514405D -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time Output buffer turn-off time Output buffer turn-off time to OE CAS to Din delay time RAS to Din delay time WE to Din delay time OE pulse width Turn-off to RAS Turn-off to WE Output data hold time Output data hold time from RAS Read command hold time from RAS Read command hold time from CAS Read command hold time from column address Symbol t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t CAL t OFF1 t OFF2 t CDD t RDD t WDD t OEP t OFR t WEZ t OH t OHR t RCHR t RCHC t RCHA Min -- -- -- -- 0 0 0 30 18 -- -- 15 15 15 15 -- -- 5 5 60 15 30 Max 60 15 30 15 -- -- -- -- -- 15 15 -- -- -- -- 15 15 -- -- -- -- -- -7 Min -- -- -- -- 0 0 0 35 23 -- -- 18 18 18 18 -- -- 5 5 70 18 35 Max 70 18 35 18 -- -- -- -- -- 15 15 -- -- -- -- 15 15 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6, 21 6 6, 21 6 18 18 Notes 2, 3, 17 3, 4, 13, 17 3, 5, 13, 17 3, 17
8
HM514405D Series
Write Cycle
HM514405D -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 10 10 10 10 0 10 Max -- -- -- -- -- -- -- -7 Min 0 13 10 13 13 0 13 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 11 11 Notes 10
Read-Modify-Write Cycle
HM514405D -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 133 77 32 47 15 Max -- -- -- -- -- -7 Min 159 90 38 55 18 Max -- -- -- -- -- Unit ns ns ns ns ns 10 10 10 Notes
Refresh Cycle
HM514405D -6 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol t CSR t CHR t RPC t CPN Min 10 10 10 10 Max -- -- -- -- -7 Min 10 10 10 13 Max -- -- -- -- Unit ns ns ns ns Notes
9
HM514405D Series
EDO Page Mode Cycle
HM514405D -6 Parameter EDO page mode cycle time EDO page mode CAS precharge time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Symbol Min t HPC t CP t RASC t ACP t RHCP t DOH t COL t COP t RCHP 25 10 -- -- 35 3 10 5 35 Max -- -- -7 Min 30 13 Max -- -- Unit ns ns 12 3, 13, 17 Notes 22
100000 -- 35 -- -- -- -- -- -- 40 3 13 5 40
100000 ns 40 -- -- -- -- -- ns ns ns ns ns ns
EDO Page Mode Read-Modify-Write Cycle
HM514405D -6 Parameter EDO page mode read-modify-write cycle time EDO page mode read-modify-write cycle CAS precharge to WE delay time Symbol t HPCM t CPW Min 66 52 Max -- -- -7 Min 77 60 Max -- -- Unit ns ns 10 Notes
Test Mode Cycle*16
HM514405D -6 Parameter Test mode WE setup time Test mode WE hold time Symbol t WS t WH Min 0 10 Max -- -- -7 Min 0 10 Max -- -- Unit ns ns Notes
10
HM514405D Series
Notes: 1. AC measurements assume t T = 2 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 4. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF1 (max), tOFF2 (max), tOFR (max) and tWEZ (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD, t CPW and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), tCPW tCPW (min) and tAWD tAWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among t AA , t CAC and t ACP. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 2-bit test function controlled by control address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the cond-tion of the output data is low level. In order to end this test mode operation, perform a RAS-only refresh cycle or a CASbefore-RAS refresh cycle. 17. In a test mode read cycle, the value of tRAC , t AA , t CAC , t OAC and t ACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. Either t RCH or tRRH must be satisfied 19. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 20. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle.
11
HM514405D Series
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS CAS between tOHR and t OH, tOFR and t OFF. 22. t HPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle tHPC (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. 23. t CSH (min) can be achieved when tRCD tCSH (min) - tCAS (min). 24. XXX H or L (H: V IH (min) V IN V IH (max), L: VIL (min) V IN V IL (max)) /////// Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.
12
HM514405D Series
Timing Waveforms *24
Read Cycle
t RC t RAS
RAS tT t RCD t RSH t CAS t CSH t RP t CRP
CAS t RAD t ASR t RAH t ASC t RAL t CAH
Address
Row
Column t CAL t RCS t RCHR t RCHC t RCHA t OH t OHR t RCH t RRH t CAC t AA t OFR t OFF1 Dout t RAC t DZC t OAC High-Z t WDD t DZO t OEP t ODD t OFF2 t CDD t WEZ t RDD
WE
Dout
Din
OE
13
HM514405D Series
Early Write Cycle
t RC t RAS
RAS tT t RCD t CSH CAS t RSH t CAS
t RP t CRP
t ASR
t RAH
tASC
t CAH
Address
Row
Column
t WCS
t WCH
WE
t DS
t DH
Din
Din
Dout
High-Z*
* t WCS
t WCS (min)
14
HM514405D Series
Delayed Write Cycle*15
t RC t RAS
t RP
RAS t CSH t RCD tT t RSH t CAS t CRP
CAS t ASR t RAH t ASC t CAH Column t CWL t RWL
Address
Row
, + * $
t RCS t WP WE t DS t DH Din High-Z Din t DZC t DZO t ODD t OEH Dout
Invalid Dout*
t OFF2
OE
*
* Invalid Dout comes out, when OE is low level.
15
HM514405D Series
Read-Modify-Write Cycle
t RWC t RAS
t RP
RAS tT t RCD t CAS t CRP
CAS t RAD t ASR t RAH t ASC tCAH
Address
Row t RCS
Column t CWD t AWD t CWL t RWL t WP
WE t RWD t RAC t DZC Din
High-Z
t AA t CAC t DS t DH
Din
Dout t OAC
Dout
t OFF2 t DZO OE t OEP t ODD
t OEH
16
HM514405D Series
RAS-Only Refresh Cycle
t RC t RAS t RP
RAS tT t CRP CAS t RPC t CRP
t RAH t ASR Address Row
Dout
High-Z
17
HM514405D Series
CAS-Before-RAS Refresh Cycle
t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP
, , + * $
t CPN t WS t WH t CPN WE Address t OFR t OFF1 Dout High-Z 18
HM514405D Series
Hidden Refresh Cycle
tRC t RAS
(Read)
t RC t RP t RAS
(Refresh)
t RC t RP t RAS
(Refresh)
tRP
RAS tT t RSH t RCD CAS t ASC t ASR t RAD t RAH Address Row t RAL t CAH Column t RCH t RRH t OHR t CAC t AA t RAC Dout t DZC t OFF2 t CDD Din tDZO t OAC High-Z t ODD t RDD Dout t WEZ t WDD t OFF1 t OH t CAS t CHR t CRP
t RCS WE
OE
19
HM514405D Series
EDO Page Mode Read Cycle (tHPC minimum cycle operation)
t RASC t RHCP t RP
RAS tT t CSH t RCD CAS t ASR t RAD t RAH Address Row tASC t CAL t CAH Column 1 t CAL t ASC t CAH Column 2 t ASC t CAL t RAL t CAH Column 3 t RCHA t RCS WE t DZC t WEZ t CDD Din t CAC t RAC t AA High-Z t CAC t AA t ACP t DOH Dout t OAC t DZO t OFF2 Dout 1 t CAC t AA t ACP t DOH Dout 2 t OFR t RCHP t RCHC t RRH t RCH t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
t OH t ODD t OHR
t OFF1 Dout 3
OE
20
HM514405D Series
EDO Page Mode Read Cycle (High-Z control by WE and OE)
t RP RAS tT CAS t RCS WE tASR Address tRAH t ASC Row tDZC
Din
t RASC t CSH t CAS t RCHR t RCHC t RCHA tCAH t ASC t CAH
Column 2
t HPC t HPC tCAS t RCHP t RHCP t CP tCAS t RRH t RCH t t RAL RCHC t ASC t CAH
Column 3
t CP
t HPC t CAS
t CRP
t CP
t RCH t RCS
tASC
t CAH
Column 4
t WDD
Column 1 tCAL High-Z tDZO
t CAL
t CAL
t CAL
tRDD tCDD
tCOL
tCOP tODD
OE tOAC tCAC tAA tRAC Dout tACP tAA tCAC tWEZ tOFF2 tOAC Dout 2 tACP tACP tAA tCAC tDOH Dout 2
Dout 3
tAA tOFF2 tCAC tOAC Dout 4
tOFR tOHR tOFF2 tOFF1 tOH
Dout 1
21
HM514405D Series
EDO Page Mode Early Write Cycle (tHPC minimum cycle operation)
t RASC t RP
RAS tT t CSH t RCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS
t ASR
t RAH
t ASC
t CAH
t ASC
t CAH
t ASC
t CAH
Address
Row
Column
Column
Column
t WCS
t WCH
t WCS
t WCH t WCS
t WCH
WE
t DS
t DH
t DS
t DH
t DS
t DH
Din
Din
Din
Din
Dout
High-Z
22
HM514405D Series
EDO Page Mode Delayed Write Cycle*15
t RASC t RP
RAS tT t CSH tRCD t CAS t CP t HPC t CAS t CP t RSH t CAS t CRP
CAS t ASR t RAH t ASC t CAH Column t CWL t RCS t WP WE t DH t DS t RCS t DS t DH t RCS t DS Din t DH t ASC t CAH t ASC t CAH
Address
Row
Column t CWL t WP
Column t CWL t WP t RWL
Din
Din
Din t OEH
Dout t ODD
High-Z
OE
23
HM514405D Series
EDO Page Mode Read-Modify-Write Cycle*15
t RASC RAS t RCD tT t CAS CAS t RAD t RAH t ASR t CAH t ASC t ACP t ASC t CAH t CAH t ASC t CP t CAS t HPCM t CP t CAS t CRP t RP
Address
Row
Column t AWD t CWD t RWD t CWL t WP t RCS
Column t AWD t CWD t CPW t CWL t WP
Column t CPW t AWD t RCS t CWD t CWL t RWL t WP
t RCS
WE t CAC t DS t DH High-Z tAA t RAC tOAC Dout t DZO Dout t OFF2 t DZO t OEH t OAC Dout t OFF2 t OEH t DZC t CAC t DS t DH t ACP t DZC High-Z t CAC t AA t OAC Dout t OFF2 t OEH t DS t DH
t DZC
Din
Din
High-Z t AA
Din
Din
t DZO
OE t ODD t OEP t OEP t ODD tOEP t ODD
24
HM514405D Series
EDO Page Mode Mix Cycle (1)*22
t RP RAS tT CAS t WCS WE tASR Address Row t ASC tRAH tCAH t ASC t CAH Column 2 t CAL High-Z tODD OE t ACP tAA tOAC tCAC tDZO t ACP tAA tCAC t DOH Dout Dout 2
Dout 3
t RASC t CSH t CAS t WCH tCPW tAWD tASC t CAH Column 3 t CAL t DS t DH tWP tASC t CP t CAS t CP tCAS t CP tCAS t RCHP t RCHC t RCHA t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH t CRP
Column 1 tCAL t DH Din 1
t DS
Din
Din 3 tWDD
tACP tAA tCAC tOAC
tOFR tWEZ tOFF2 tOFF1 tOH Dout 4
tOFF2
25
HM514405D Series
EDO Page Mode Mix Cycle (2) *22
t RP RAS tT CAS t RCS WE tASR Address Row t ASC tRAH tCAH t ASC t CAH Column 2 t DS
Din
t RASC t CSH t CAS t RCHR t RCH t WCS t WCH tCPW t ASC t CAH Column 3 t CAL t DS t DH t CP t CAS t CP tCAS tCWL tWP tASC t CP tCAS t RCHP t RCHC t RCHA t RAL t CAH Column 4 t CAL tRDD tCDD t RRH t RCH t CRP
Column 1 tCAL High-Z
t CAL t DH Din 2
Din 3 tDZO tODD tDZO tWDD
tODD OE tAA tOAC tCAC tRAC
tOFF2
t OAC tACP tAA tCAC
tACP tOFF2 tAA tCAC tOAC
tOFR tWEZ tOFF2 tOFF1 tOH Dout 4
Dout
Dout 1
Dout 3
26
HM514405D Series
Test Mode Cycle
*,** Reset Cycle
Set Cycle**
Test Mode Cycle
Normal Mode
RAS
CAS
WE
* CBR or RAS-only refresh ** Address, Din, OE: H or L
27
HM514405D Series
Test Mode Set Cycle WE-and-CAS-Before RAS-Refresh Cycle
t RC t RP t RAS t RP
RAS t RPC t CSR tT CAS t CPN t WS t WH t CPN t CHR t RPC t CRP

WE Address t OFF1 t OFR Dout High-Z 28
HM514405D Series
Package Dimensions
HM514405DS Series (CP-26/20D)
Unit: mm
26
16.90 17.27 Max 22 18
14
7.62 0.13
1
3.50 0.26
5 0.74 1.30 Max
9
13
0.21 2.40 + 0.24 -
8.51 0.13 0.80 +0.25 -0.17
6.71 0.28
Hitachi Code JEDEC Code EIAJ Code Weight CP-26/20D MO-077-AA SC-633A 0.6 g
0.43 0.10 0.41 0.08
5.08 0.10
1.27
29
HM514405D Series
HM514405DTT Series (TTP-26/20D)
Unit: mm
17.14 17.54 Max 26 22 18 14 7.62 1 5 1.27 0.42 0.08 0.40 0.06 0.21 1.15 Max 0.17 0.05 0.125 0.04 0.13 0.05 1.20 Max 5.08 0.10 0 - 5 0.50 0.10
M
9
13
0.80 9.22 0.20
Hitachi Code JEDEC Code EIAJ Code Weight
TTP-26/20D MO-132AA -- 0.32 g
30
HM514405D Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
31
HM514405D Series
Revision Record
Rev. Date 0.0 Contents of Modification Drawn by Approved by Dec. 12, 1996 Initial issue
32

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